The present invention relates to a semiconductor device having such elements as a capacitor, a resistor, and a transistor mounted thereon, of which high integration and low cost are required.
A manufacturing process for a conventional semiconductor device having a MOS transistor, a capacitor, and a resistor mounted thereon (combined analog and digital circuit) has been implemented by a normal manufacturing process for the MOS transistor (process for digital devices) combined with an additional manufacturing process for the capacitor and resistor (process for analog devices).
In a MOS transistor formed recently by the normal manufacturing process for digital devices, it has become necessary to reduce the resistance of the gate electrode and source/drain diffusion layers by forming a polycide gate or salicide or selectively growing a metal material, thereby increasing the operating speed of the transistor and reducing the area occupied thereby.
On the other hand, a resistor formed by the process for analog devices should be composed of a high-resistance material to occupy a reduced area as well as have accurately controlled resistance. The resistor is normally formed by using a diffusion layer formed simultaneously with the source/drain regions of the MOS transistor, a polysilicon layer which is to form the gate of the MOS transistor, or either one layer of a two-layer polysilicon electrode forming a capacitor. However, since the demand for a higher-speed, smaller-area MOS transistor has reduced the resistance of the gate electrode and source/drain diffusion layers as described above, the area occupied by the resistor will be increased if the desired resistance is imparted thereto, which leads to the problem that the area occupied by the whole semiconductor device cannot be reduced.
To prevent the problem, there has conventionally been proposed such a method as disclosed in U.S. Pat. No. 4,949,153, wherein an insulating film is formed on a region intended to have relatively high resistance prior to silicidization in a salicide process, which allows a layer with relatively high resistance to be formed simultaneously with the formation of a low-resistance layer. The process of manufacturing an N-channel MOS transistor and a resistor discussed in the foregoing publication will be described with reference to FIGS. 10(a) to 10(g).
First, in the step shown in FIG. 10(a), an isolation 22 is formed by a process of, i.e., trench isolation in a P-well 21 formed in a silicon substrate. Subsequently, a first insulating film 23 composed of a silicon oxide film is formed by, e.g., pyrogenic oxidation, followed by a polysilicon film deposited by, e.g., CVD to serve as a resistor. Thereafter, arsenic ions are implanted in the polysilicon film, which is subjected to a thermal treatment for activation. Thereafter, a desired resist film (not shown) is formed and used as a mask in dry etching for patterning the polysilicon film into a first conductor film 24.
Next, as shown in FIG. 10(b), the first insulating film 23 is removed by wet etching and a gate oxide film 25a is formed. During the formation step, a second insulating film 25b composed of an oxide film is also formed on the top and side surfaces of the first conductor film 24. However, since polysilicon is more likely to be oxidized than single-crystal silicon, the second insulating film 25b is thicker than the gate oxide film 25a. Thereafter, a second conductor film 26 composed of a polysilicon film is deposited by, e.g., CVD to form a gate electrode. After that, arsenic ions are implanted in the second conductor film 26.
Next, as shown in FIG. 10(c), the second conductor film 26 is patterned by dry etching using the desired first resist film 27 as a mask to form a gate electrode 26a. 
Next, as shown in FIG. 10(d), impurity ions are implanted in the P-well 21 to form N-type low-concentration diffusion layers 29, which are to serve as N-type LDD (Lightly Doped Drain) layers, followed by a silicon oxide film 28 deposited by, e.g., CVD to serve as a sidewall insulating film. The silicon dioxide film 28 forms sidewalls for the MOS transistor as well as a protective film from silicidization in the subsequent step. At this stage, a second resist film 35 is formed on the silicon oxide film 28 to correspond to the region with high resistance of the first conductor film 24 composing the main portion of a resistor.
Next, as shown in FIG. 10(e), anisotropic etching is performed by using the second resist film 35 as a mask to remove the silicon oxide film 28, which is partially left on the side surfaces of the gate electrode 26a of the MOS transistor and on the side surfaces of the first conductor film 24 that is to serve as the resistor, to form sidewall insulating films 28a. The silicon oxide film 28 is also left on the region previously covered by the resist film 35 as the mask to form an on-resistor insulating film 28b. Impurity ions are further implanted in the P-well 21 to form N-type high-concentration diffusion layers 30, which are to serve as the source/drain regions, and subjected to a thermal treatment for activation.
Next, as shown in FIG. 10(f), a high-melting-point metal such as titanium is deposited and subjected to a rapid-heating thermal treatment so that silicide films 31 composed of a reaction product of silicon and titanium are formed on regions uncovered with the silicon oxide film and composed of silicon, in which the surfaces of the gate electrode 26a, N-type high-concentration layers 30, and first conductor film 24 are exposed. After that, the unreacted portions of the titanium film unformed with the silicide films 31 are removed by wet etching.
Next, as shown in FIG. 10(g), an interlayer insulating film 32, CW contacts 33, metal interconnect layers 34 are formed sequentially on the substrate, resulting in the semiconductor device on which the N-channel MOS transistor having the low-resistance gate, source, and drain and the resistor composed of the high-resistance region are mounted.
Although the foregoing embodiment has used the two-layer polysilicon film consisting of the first and second conductor films 24 and 26, it is also possible to use the second conductor film 26, which is to form the gate of the MOS transistor, to compose the first conductor film 24 that is to serve as the resistor. However, since trends have required higher capacitance from a capacitor used in an analog circuit, it is preferred in the future to use a capacitor having a two-layer conductor film such that an insulating film between the two layers is used as a capacitor (2PS capacitor).
Next, a description will be given to a prior art related to the plan configuration of the resistor.
As shown in FIG. 11(a), the resistor typically has a meander plan configuration composed of a conductor film bent back several times. Specifically, linear portions 36b and fringe portions 36c corresponding to the bent portions alternate between contact formation regions 36a at both ends. However, the presence of the fringe portions 36c, which is varied in configuration, causes variations in resistance and in spreading resistance. As a result, the accuracy of the resistor is lowered even when a specified resistance value is intended for the resistor.
To eliminate the problem, there may be cases where the following method is implemented. As shown in FIG. 11(b), the resistor 36 is composed of the plurality of discrete linear portions 36b parallel with each other. Both ends of the linear portions 36b are formed with the respective CW contacts 33 to be connected to the upper metal interconnect layers 34. Each adjacent two of the linear portions have their ends connected to each other via the two CW contact layers 33 and the metal interconnect layers 34 so as to constitute the whole single resistor. The resistor thus constituted is for preventing variations in resistance, since no bent portion is included therein. However, the foregoing manufacturing method for the conventional resistor and the structure thereof present the following problems.
To form the high-resistance region not to be silicidized in the polysilicon film composing the first conductor film 24, the foregoing manufacturing method shown in FIGS. 10(a) to 10(g) requires an additional lithographic step, which increases the number of manufacturing steps.
In the structure of the resistor shown in FIG. 11(b), the resistance of the CW contacts 33 causes variations in the resistance of the whole structure, resulting in lower accuracy of the resistance. In addition, the area occupied by the whole resistor is increased by regions with margins to be connected to the CW contacts 33, which should be provided on both ends of each of the linear portions 36b. 
A first object of the present invention is to provide a semiconductor device having a transistor and a passive component mounted thereon and a method of manufacturing the same, wherein the mounted passive component exhibits an excellent property without incurring an increase in cost resulting from an increased number of manufacturing steps and an increase in the area occupied thereby.
A second object of the present invention is to provide a semiconductor device having a resistor composed of linear portions and a bent portion mounted thereon, wherein the mounted resistor has accurately controlled resistance with means for eliminating a variation in the resistance of the bent portion.
A first semiconductor device according to the present invention comprises: a first conductor member formed on a part of a semiconductor substrate and having a contact formation region; a second conductor member covering the first conductor member except for the contact formation region; an insulating film interposed between the first and second conductor members; and a low-resistance layer formed in contact with a surface of the contact formation region of the first conductor member and with a surface of the second conductor member, the semiconductor device being capable of selecting at least one of an inductor, a resistor, and a capacitor and allowing the selected one to function by using the first and second conductor members and the insulating film.
The structure enables a reduction in the resistance of the contact formation region of the first conductor member as well as a reduction in the resistance of the second conductor member. When only the first conductor member is allowed to function, an inductor or resistor with desired resistance is obtained. On the other hand, when the first conductor member, the insulating film, and the second conductor member are allowed to function, a capacitor using the first conductor member as the lower electrode, the insulating film as the capacitor insulating film, and the second conductor member as the upper electrode is obtained. Consequently, it becomes possible to selectively mount an inductor, a resistor, and a capacitor on a semiconductor device such that a capacitor is provided at one portion, a resistor or an inductor is provided at another portion, and a resistor or a capacitor is provided at still another portion as desired. Since the capacitor and resistor or the capacitor and inductor are provided overlapped at the same portion when viewed in two dimensions, the area occupied by the components remains small.
The first semiconductor device further comprises a MOS transistor having a gate electrode formed on the semiconductor substrate and source/drain regions formed by introducing an impurity into regions of the semiconductor substrate located on both sides of the gate electrode, wherein another low-resistance layer composed of the same material as the low-resistance layer on the first conductor member is formed in contact with a surface of at least the gate electrode of the gate electrode and source/drain regions.
The structure enables a MOS transistor having a lower-resistance gate electrode or a MOS transistor having a low-resistance gate electrode and low-resistance source/drain regions, a resistor, an inductor, or a capacitor to be mounted on the same substrate, so that the resulting semiconductor device has extremely wide applications.
The first conductor member may be composed of an impurity diffusion layer formed in the semiconductor substrate and the second conductor member may be composed of a polysilicon film.
The structure enables the manufacturing of the semiconductor device by a single-layer polysilicon process, resulting in low manufacturing cost.
The first conductor member may be composed of a first polysilicon film formed on the semiconductor substrate and the second conductor member may be composed of a second polysilicon film formed above the first polysilicon film.
The structure enables the formation of the semiconductor device by a two-layer polysilicon process and provides a capacitor of MIM structure, so that the capacitance property of the resulting capacitor exhibits substantially no dependence on voltage. Moreover, since the resistor is also composed of polysilicon, the resistance of the resistor can be controlled more easily and accurately than in the case where the resistor is composed of the semiconductor substrate.
The low-resistance layer may be composed of a metal silicide film.
The structure enables the formation of a transistor and a passive component each having an excellent resistance property by using a polycide process or salicide process.
The low-resistance layer may also be composed of a low-resistance metal film selectively deposited on the first conductor member and on the second conductor member.
The first semiconductor device further comprises a dummy conductor member arranged in parallel with the first conductor member on the semiconductor substrate and having a contact formation region.
In the structure, the first conductor member and the dummy member form a line-and-space pattern, so that the configuration of the first conductor member is improved in accuracy in a photolithographic step.
The dummy member has a potential which can be fixed to a specified value via the contact formation region.
The structure prevents the voltage of the first conductor member from becoming unstable due to the presence of the dummy member.
A second semiconductor device according to the present invention comprises: a first conductor member formed on a part of a semiconductor substrate and having a contact formation region, the first conductor member having a linear configuration composed of a plurality of linear portions and at least one bent portion connecting the linear portions in a plane parallel with a surface of the semiconductor substrate; an insulating film covering the first conductor member except for the contact formation region and the bent portion; and a low-resistance layer formed in contact with a surface of the contact formation region of the first conductor member and with a surface of the bent portion of the first conductor member.
In the structure, the resistance of the bent portion is extremely lowered in the case where the first conductor member functions as a resistor or an inductor. Accordingly, the resistance of the resistor or inductor is substantially determined by the resistance of the linear portions so that a variation in the resistance of the bent portion exerts a slight influence on the resistance of the whole resistor. Moreover, there is no accuracy degradation resulting from variations in the resistance of a contact member or the like serving as a detour around the low-resistance contact and interconnect layer at the bent portion of the resistor or inductor. What results is a high-accuracy resistor or inductor of extremely simple structure.
The linear portions of the first conductor member may be parallel with each other and the first conductor member may have a meander configuration.
The second semiconductor device further comprises a second conductor member formed to extend over all the linear portions of the first conductor member; and another low-resistance layer formed in contact with a surface of the second conductor member and composed of the same material as the low-resistance layer on the first conductor member such that the semiconductor device is capable of selecting at least one of an inductor, a resistor, and a capacitor and allowing the selected one to function by using the first and second conductor members and the insulating film.
The first conductor member may be configured as a polygonal helix extending outwardly from a center end thereof and terminating at an outer end thereof such that the plurality of linear portions of the first conductor member correspond to individual sides of the polygonal helix and that the bent portion of the first conductor member corresponds to a vertex of the polygonal helix.
The second semiconductor device further comprises: a second conductor member composed of a conductor material and formed into distinct segments each extending over the linear portions parallel with each other and located on the same side relative to the center end of the first conductor member configured as the polygonal helix; and another low-resistance layer formed in contact with a surface of the second conductor member and composed of the same material as the low-resistance layer on the first conductor member such that the semiconductor device is capable of selecting at least one of an inductor, a resistor, and a capacitor and allowing the selected one to function by using the first and second conductor members and the insulating film.
The structure suppresses an increase in the area occupied by the first conductor member which has been sufficiently elongated to achieve high resistance. What results is a structure which allows easy control of resistance and inductance without increasing the area occupied thereby.
The segments of the second conductor member have respective contact regions extending outwardly of the outermost ones of the linear portions of the first conductor member and the second semiconductor device further comprises: a plurality of interconnect layers formed above the first and second conductor members with an interlayer insulating film interposed therebetween; a first connecting member for connecting the individual interconnect layers to the contact formation region of the first conductor member; and a second connecting member for connecting the individual interconnect layers to a plurality of portions of the contact formation region of the second conductor member such that a signal delay circuit is formed between the first and second connecting members.
The structure implements a delay circuit which allows a delay property to be controlled over a wide range while suppressing the attenuation of a signal.
The second semiconductor may further comprise a dummy conductor member arranged in parallel with the outermost ones of the linear portions of the first conductor member on the semiconductor substrate and having a contact formation region and the dummy member preferably has a potential fixed to a specified value via the contact formation region.
A first method of manufacturing a semiconductor device according to the present invention comprises: a first step of forming a first conductor member on a semiconductor substrate having at least a passive component formation region; a second step of forming an insulating film on at least the first conductor member; a third step of depositing a conductor film covering at least the insulating film; a fourth step of patterning the conductor film to form a second conductor member covering the conductor film except for at least a contact formation region thereof; and a fifth step of forming a low-resistance layer on an exposed surface of the first conductor member and on a surface of the second conductor member, wherein the first conductor member, the second conductor member, and the insulating film form at least one of an inductor, a resistor, and a capacitor in the passive component formation region.
The method allows a reduction in the resistance of only the contact formation region without reducing the resistance per unit length of the first conductor member. As a result, a resistor and an inductor having a desired resistance property is formed in a reduced number of steps without increasing the area occupied thereby.
The semiconductor substrate may further be provided with an active component formation region, the second step may include forming the insulating film also on the semiconductor substrate in the active component formation region, the third step may include depositing the conductor film also on the insulating film in the active component formation region, the fourth step may include patterning the conductor film and the insulating film to form a gate insulating film and a gate electrode therefrom in the active component formation region, and the fifth step may include forming the low-resistance layer on a surface of at least the gate electrode in the active component formation region.
The methods provides a manufacturing process combining a digital process with an analog process, which enables the formation of a semiconductor device having an active component and a variety of passive components mounted thereon.
The first method of manufacturing a semiconductor device further comprises a step of forming an isolation on the semiconductor substrate such that the isolation surrounds the active component formation region, wherein the first step may include depositing a first polysilicon film on the isolation and patterning the first polysilicon film to form the first conductor member, the second step may include oxidizing a surface of the semiconductor substrate in the active component formation region and a surface of the first conductor member in the passive component formation region to form the insulating film, and the third step may include forming a second polysilicon film as the conductor film.
The method enables the formation of a high-accuracy capacitor and a resistor or an inductor with resistance that can be controlled over a wide range by a process combined with a two-layer polysilicon process used generally as a digital process for forming a semiconductor device having a MOS transistor mounted thereon.
The first method of manufacturing a semiconductor device further comprises a step of forming an isolation on the semiconductor substrate such that the isolation surrounds the active component formation region and the passive component formation region, wherein the first step may include introducing an impurity into the semiconductor substrate in the passive component formation region to form the first conductor member, the second step may include oxidizing a surface of the semiconductor substrate in the active component formation region and a surface of the first conductor member in the passive component formation region to form the insulating film, and the third step may include forming a polysilicon film as the conductor film.
The method enables the formation of a semiconductor device having a passive component and an active component mounted thereon by a simple process combined with a single-layer polysilicon process used generally as a digital process for forming a semiconductor device having a MOS transistor mounted thereon.
The first step may include forming a dummy member composed of the same material as the first conductor member in parallel with and outside the first conductor member, the second step may include forming the insulating film also on the dummy member, the fourth step may include forming the second conductor member and a capacitor insulating film each covering the dummy member except for a contact formation region thereof, and the fifth step may include forming the low-resistance layer also on an exposed surface of the dummy member.
In accordance with the method, the first conductor member and the dummy member form a line-and-space pattern, so that the configuration of the first conductor member is improved in accuracy in a photographic step. Moreover, since the contact formation region is also provided in the dummy member, the voltage of the dummy member can be fixed by connecting the dummy member to the upper interconnect layer. This prevents variations in the electric properties of the semiconductor device resulting from the presence of the dummy member in the electrically floating state.
A second method of manufacturing a semiconductor device according to the present invention comprises: a first step of forming, on a part of a semiconductor substrate, a first conductor member having a linear configuration composed of a plurality of linear portions parallel with each other in a plane parallel with a surface of the semiconductor substrate and bent portions connecting the individual linear portions; a second step of forming an insulating film covering a surface of at least the first conductor member; a third step of patterning the insulating film to form a capacitor insulating film covering the first conductor member except for a contact formation region and the bent portions thereof; and a fourth step of forming a low-resistance layer on an exposed surface of the first conductor member.
The method enables the formation of the resistor or inductor having low resistance at the bent portion. The resulting resistor or inductor has a stable resistance property with minimum resistance variations resulting from resistance variations at the bent portion.
In the second method of manufacturing a semiconductor device, there can be performed the process for implementing the foregoing second semiconductor device.